For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...

Just like production code, test code needs to be rigorously examined to ensure it’s clean and bug free. In this first half of a two-part article, Klaus Berg makes the case for why good unit tests are ...

PARTNER CONTENT: Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original ...

Skip the brand hype. A capability-by-capability breakdown of AI testing tools, self-healing, NLP authoring, visual, ...